Non-volatile electrically erasable integrated circuit memory devices can be categorized as EEPROMs and as "flash" EPROMs (also called flash EEPROMs). EEPROMs utilize the well-known Fowler-Nordheim tunneling mechanism for both programming and erasing. Flash EPROMs, on the other hand, utilize hot electron injection for programming and Fowler-Nordheim tunneling for erasing.
Flash memory devices are typically composed of one or more arrays of single transistor flash EPROM cells. Each cell includes a source, a drain, a control gate, and a floating gate. Through a series of rows and columns, each flash cell can be erased, programmed, or read.
In order to operate at high speeds, a flash memory device places certain demands on row driving circuits. For example, during a read operation the row driving circuit must be capable of driving the row between +0 volts and +5 volts in only a few nanoseconds. The same row driving circuits must also be capable of driving the row to +12 volts or -12 volts in only a matter of microseconds during program and erase. Thus, the row driving circuit speed is an essential aspect of flash EPROM operation.
Large, high-speed flash memories also exact a toll on cell capacity. In order to accomplish high speed operation in flash memories, complex column and row decoding and driving circuits are often required, which can occupy valuable area on the integrated circuit, reducing the potential number of cells in the array. Any reduction in the number of driving circuit devices provides more area for additional flash cells, or a more compact integrated circuit. Such a reduction can also simplify the fabrication process.
A row driving circuit for a flash EPROM is set forth in U.S. Pat. No. 5,077,691, issued to Haddad et al. on Dec. 31, 1991. The row driving circuit is reproduced in detail herein, as FIG. 1. The prior art row driving circuit is designed to operate in three modes; a READ mode, a PROGRAM mode, and an ERASE mode. In the READ mode a selected row is driven to +5 volts while a deselected row is driven to .about.0 volts. Similarly, in the PROGRAM mode, a row is selected and driven to +12 volts while deselected rows are driven to .about.0V. In the ERASE mode, all rows are normally driven to -12 volts, while a small number of rows may be disabled from ERASE by being driven to +5 volts. The operating conditions of the prior art circuit are set forth below in Table I below.
TABLE I ______________________________________ MODE XIN X S1 S2 S3 ______________________________________ Read Select .about.0 V +5 V +5 V .about.0 V -2 V Read Disable +5/ +5/.about.0 V +5 V .about.0 V -2 V .about.0 V Program Select .about.0 V +5 V +12 V +5 V -2 V Program Disable +5/ +5/.about.0 V +12 V +5 V -2 V .about.0 V Erase Select +5 V +5 V +5 V .about.0 V 5 V Erase Disable .about.0 V +5 V +5 V .about.0 V 5 V ______________________________________ MODE S4 V1 V2 V3 ______________________________________ Read Select +5 V .about.0 V +5 V +5 V Read Disable +5 V +5 V .about.0 V .about.0 V Program Select float .about.0 V +12 V +12 V Program Disable float +12 V .about.0 V .about.0 V Erase Select .about.13 V +5 V .about.-12 V .about.0 V Erase Disable .about.13 V .about.0 V +5 V float ______________________________________
As set forth in FIG. 1, the prior art row driving circuit includes a NMOS input transistor that acts as a passgate upon the application of a decode signal X and inverted decode signal XIN. The drain of the NMOS input transistor is connected to node V1 which includes the drain of a PMOS input pull-up transistor, the gate of a PMOS row pull-up transistor, and the gate of an NMOS row pull-down transistor. The sources of both PMOS pull-up transistors are connected to a positive supply voltage via S1. Depending on the mode, as set forth in Table 1 above, S1 is alternatively at +5 volts or +12 volts. The gate of the input pull-up PMOS transistor is switched between different bias voltages by S2, also according to the mode. One skilled in the art would recognize that combination of the NMOS input transistor and PMOS input pull-up transistor, along with the decoder signals X and XIN, act as a level shifter. When a row is selected, the NMOS input transistor sinks more current than the PMOS input pull-up transistor can source, pulling node V1 low. If the input is not sinking current, the PMOS input pull-up transistor is biased to pull node V1 to the voltage at S1.
As set forth in FIG. 1, the row (set forth as node V2) is driven by the PMOS row pull-up transistor and the NMOS row pull-down transistor which operate as a CMOS inverter. When V1 is at .about.0 volts, the NMOS row pull-down transistor is cut off, and the PMOS row pull-up transistor pulls the row (V2), up to the voltage of S1. This "selects" the row for reading and for programming. When V1 is pulled up to the same voltage as S1 by the level shifter, the PMOS row pull-up transistor is cut-off, and the NMOS row pull down transistor pulls the row down to .about.0 volts. This deselects the row during reading and programming.
Interposed between the transistors of the inverter formed by row pull-up and pull-down transistors is a PMOS isolation transistor. The PMOS isolation transistor is positioned between the drain of the NMOS row pull-down transistor and the row. In the READ and PROGRAM modes, the gate of the isolation PMOS transistor receives the voltage determined by S3. As set forth in Table I, in the READ and PROGRAM modes, the gate of the PMOS isolation transistor is at -2 volts which ensures the transistor is on, allowing the row to be pulled to 0 volts. In contrast, in the ERASE mode, S3 is set to +5 volts, isolating the NMOS row pull-down transistor from the row as is reflected at node V3. The isolation function is necessary because if the drain of the NMOS pull-down transistor was directly connected to V2, the P-N junction formed by its drain and the p-type substrate would be forward biased when the row was pulled any lower than .about.0.6 volts below ground.
As set forth in FIG. 1 and Table I, the negative erasing voltage is provided to the row by a PMOS erase transistor having its source connected to V2 and both its drain and gate connected to S4 which provides a voltage according to operation mode. This includes the negative erase voltage during the ERASE mode.
All the PMOS devices, including the PMOS erase transistor share the same n-well, which follows S1. This arrangement ensures that the P-N junctions formed by the source of the PMOS erase transistor and its n-well do not become forward biased when the row is driven above +5 volts during PROGRAM mode. As shown in Table I, S4 remains floating during the PROGRAM mode, drawing no dc current. In the READ mode S4 is held at +5 volts, which leaves the PMOS erase transistor cut-off. In ERASE mode S4 is driven to -13 volts. At the same time, S3 and node V1 are at +5 volts, cutting off both the PMOS isolation transistor and the PMOS row pull-up transistor. This allows the row to be pulled down to .about.-12 volts by the PMOS erase transistor in the ERASE mode.
In a typical ERASE procedure, the erase voltage (.about.-12 volts) is applied to a block of rows (a sector), requiring that all of the row drivers be enabled "low" together. This is accomplished by driving all of the X signals to .about.0 volts. Alternatively, all the X signals can be driven high, and the XIN signals can also all be driven high. With all X signals high, a block of rows decoded by a single XIN signal can be disabled from ERASE by driving the XIN signal low. This will disable the ERASE for those rows by holding them at +5 volts with the PMOS row pull-up transistor pulling up against the load of the PMOS erase transistor.
As mentioned previously, it is always desirable to free up area on an integrated circuit. Because the PMOS isolation transistor takes up area and serves no function other than isolation, it would be desirable to arrive at a row driving circuit that could eliminate this device. While other prior art methods have eliminated the device, it has been by utilizing a triple well process, which adds to process complexity.
In layout, the row driving circuit of Haddad et al. requires that the V1 node be connected to both gates of the row driving circuit, the NMOS pull down transistor and the PMOS pull-up transistor. The same o requirement applies to the common drain connection between the NMOS row pull-down transistor and the PMOS isolation transistor. As a result, two speed critical signals must run in the pitch of one row. Because such a constraint is particularly difficult to overcome if the manufacturing process does not use a second layer metal for interconnect, it would be desirable to eliminate this requirement.
As illustrated in FIG. 1, the lowest voltage to which the NMOS row pull-down transistor can pull a deselected row is .about.0 volts (the p-type substrate voltage). This forces a minimum erase threshold for each flash cell for a given READ operation. To provide for lower erase thresholds, it would be desirable to force the deselected rows to a lower voltage than the prior art.
It is also noted that in the Haddad et al. design, the PMOS input pull-up transistor typically has a small width-to-length (W/L) ratio relative to the NMOS input transistor, as it presents a de load which must be overpowered by the NMOS input transistor. Similarly, the PMOS erase transistor must be weak relative to the PMOS row pull-up transistor to allow the erase transistor to be overpowered by the row pull-up transistor. It would be desirable to overcome this limitation to allow for more flexibility in layout of a row driving circuit.
To the inventor's knowledge, no prior art row driving circuit is easily adaptable to single metal interconnect process, provides for lower deselect row voltages during READ operation, or allows for greater flexibility in transistor size.